The design of an integrated circuit (IC) typically includes the production of a schematic representation showing the circuit elements (termed cells) for each functional unit of the IC and the interconnections between the elements. The schematic is translated into a physical layout which is a geometric representation of the circuit composed of polygons and interconnecting paths. The layout specifies the position and relative dimensions of the layers of materials which are deposited on a silicon wafer to form the circuit elements and interconnections.
A layout for an integrated circuit typically contains a multitude of cells, with each cell or group of cells corresponding to a circuit element having a defined function (e.g., a logic gate, a multiplier, a memory cell, etc.). If the schematic for a cell is changed during the design process, then the layout for that cell must be modified to reflect the new design. "Layout versus Schematic" (LVS) verification is a procedure by which the schematic of the cell is compared to the layout to be certain that the layout properly corresponds to the functionality of the schematic. This is typically done by comparing a netlist derived form the schematic with one derived from the layout.
In addition to maintaining the proper correspondence between a schematic and the physical layout, it is also necessary that the integrated circuit design be consistent with the technology, equipment, and capabilities of the fabrication process. "Design Rule Checking" (DRC) is a process by which the layout is checked to make certain that the layout does not violate any of the geometrical relationships dictated by electrical rules and the fabrication process (metal-to-metal spacing, minimum feature width, etc.). Typically, DRC is carried out by applying DRC rules (as defined by the fabrication foundry) to a DRC program which is run on the layout database files.
During the process of designing the integrated circuit, the schematic for a cell may be changed many times. Each time the schematic is changed, the layout is also changed to reflect the new schematic. Thus, each change in a cell's schematic requires a new layout and a LVS verification. Similarly, each change in the layout (as a result of a schematic change or a change in the fabrication process) requires a DRC procedure to verify the correctness of the new layout. An IC may contain hundreds of cells, with cells being redesigned concurrently. Thus, the LVS and DRC verification procedures will be executed many times, and tracking the design stage and verification status of each cell design is an important task which can reduce the overall design time.
An alternate approach is to run the DRC and LVS procedures at the end of the overall design process. This is generally not desirable because DRC and LVS errors discovered at that time will have affected the entire design and are more difficult to fix at that point. This approach would end up requiring more time overall to implement.
Presently, information regarding the verification status of an IC design can be tabulated by hand. The disadvantage of determining the status by this method is that preparing a verification status report by hand is a slow and unreliable task. At the other extreme, while a purely automated system would speed up the process, it would not be capable of recognizing an error or inconsistency in the DRC or LVS verification processes.
What is desired is an apparatus and method for managing the tracking of the results of the DRC and LVS verification procedures used in designing an integrated circuit which is faster and more reliable than the methods currently used in the semiconductor industry.